1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a semiconductor memory device in which variations of threshold voltages of transistors constituting sense amplifiers thereof are compensated for.
2. Description of the Related Art
In a large capacity semiconductor memory device such as DRAM, etc., load capacitances of bit lines connected to sense amplifiers are increased with the recent further increase of memory capacity thereof. Such increase of the load capacitances cause an operating speed of the semiconductor memory device to be reduced. In order to solve such problem, it is usual to divide a memory cell array to a plurality of sub memory arrays to thereby reduce load capacitances of bit lines of the respective sub memory arrays, that is, sub bit lines.
On the other hand, each sense amplifier includes transistors for detecting potential levels of the sub bit lines. Necessarily, there are variations of threshold voltages of such level detecting transistors. A difference in threshold voltage between the level detecting transistors becomes a source of reduction of S/N and reduction of sensitivity since the threshold voltage difference becomes an offset voltage of the sense amplifier. Further, the variation of threshold voltage tends to increase with the increasing fineness of transistor.
On the other hand, a chip area of the semiconductor memory device has becomes about 1.5 times every generation. Although an area of memory cells can be reduced by utilizing the three dimensional structure such as trench structure and stack structure, the ratio of area occupied by the sense amplifiers to the chip area of the semiconductor memory device is increasing since the sense amplifier must use a flat structure.
Therefore, in order to realize a DRAM of giga-bit class, it is important to form high precision sense amplifiers having small area by compensating for variation of threshold voltages of the level detecting transistors constituting the sense amplifiers.
A conventional semiconductor memory device in which such variation of the threshold voltage is compensated for will be described with reference to FIG. 5 which is disclosed in Japanese Patent Application Laid-open No. Hei 5-47179. In the conventional semiconductor memory device 300 shown in FIG. 5, sense amplifiers connected to sub bit line pairs of respective sub memory cell arrays are of the direct sense system and are constructed with only NMOS transistors and bit line pairs of the respective memory cell arrays and a pair of common bit lines are formed in respective layers to form a hierarchical bit line construction.
The semiconductor memory device 300 shown in FIG. 5 comprises a memory cell array MA10 including a bit line pair (referred to as BL1, hereinafter) composed of complimentary bit lines BL11 and BL12 which are formed in parallel to each other with a small gap therebetween and a plurality of memory cells C11, C12 connected to the respective bit lines BL11 and BL12 and functioning to write data on the bit line corresponding to selected one of the memory cells C11, C12 and read the data stored in the selected memory cell onto the corresponding bit line, a memory cell array MA20 including a bit line pair BL2 composed of complimentary bit lines BL21 and BL22, memory cells C21, C22 and bit lines having the same construction and function as those of the memory cell array MA10 and arranged in registration with the respective bit lines BL11 and BL12 of the memory cell array MA10, a plurality of word lines WL11, WL12, WL21, WL22, for selecting predetermined memory cells of the memory cells included in the memory cell arrays MA10, MA20, precharge circuits PC10 and PC20 for precharging the bit line pairs BL1 and BL2 of the memory cell arrays MA10, MA20 to a precharge voltage VH which is a half of a power source voltage VD with a predetermined timing according to a precharge control signal PCS1, paired common bit lines GBL1 and GBL2 provided for the respective corresponding bit lines BL11, BL12, BL21 and BL22 of the memory cell arrays MA10, MA20, a sense amplifier SA10 for transmitting voltage levels of the bit lines BL11 and BL12 to the common bit lines GBL2 and GBL1, respectively, during a read operation and transmitting voltage levels of the common bit lines GBL1 and GBL2 to the bit lines BL11 and BL12, respectively, during a read operation and a sense amplifier SA20 constructed similarly to the sense amplifier SA10 for transmitting voltage levels of the bit lines BL21 and BL22 to the common bit lines GBL2 and GBL1, respectively, during the read operation and transmitting voltage levels of the common bit lines GBL1 and GBL2 to the bit lines BL21 and BL22, respectively, during the write operation.
The sense amplifier SA10 is composed of voltage level detecting NMOS transistors Q11 and Q21 having sources supplied with an output voltage OCV1 of a threshold voltage correcting driver circuit and gates connected to the respective bit lines BL11 and BL12, threshold voltage correcting NMOS transistors Q12 and Q22 having gates supplied with a threshold voltage correction control signal CVT1, sources connected to drains of the respective transistors Q1 and Q21 and drains connected to the respective bit lines BL11 and BL12, read NMOS transistors Q12 and Q23 having gates supplied with a read control signal RS1, ones of source drains connected to the drains of the respective transistors Q11 and Q21 and the others of the source drains connected to the respective common bit lines GBL2 and GBL1 and write transistors Q14 and Q24 having gates supplied with a write control signal WS1, ones of source drains connected to the respective common bit lines GBL1 and GBL2 and the others of the source drains connected to the respective bit lines BL11 and BL12.
Now, an operation of the semiconductor memory device 300 shown in FIG. 5 will be described with reference to a timing chart shown in FIG. 6. As shown in FIG. 6, one cycle of the operation of the semiconductor memory device 300 can be roughly divided to a precharge period T1, a threshold value correcting period T2, a read period T3 and a re-write period T4.
In the precharge period T1, the precharge circuit PC10 responds to an active level of the precharge control signal PCS1 to precharge the bit lines BL11 and BL12 to the precharge voltage VH which is a half of the power source voltage VD.
Then, in the threshold voltage correcting period T2, the precharge control signal PCS is made inactive to make the precharge circuit PC10 inactive and, simultaneously, a threshold voltage correction control signal CVT1 is set to H level. In response to the change of the threshold voltage correction control signal CVT1 to the H level, the transistors Q12 and Q22 of the sense amplifier SA10 are turned on to diode-connect the transistors Q11 and Q21. Simultaneously therewith, a reference correction voltage OCV1 is set to a correction level to correct voltage levels of the bit lines BL11 and BL12 to voltages corresponding to the threshold voltages of the respective transistors Q11 and Q21.
In the read period T3 subsequent to this threshold voltage correction, one of the word lines, for example, the word line WL11, is set to a selection level and a data stored on a memory cell C11 is read out to the bit line BL11. Simultaneously, the threshold voltage correction control signal OCV1 is set to a reference level. The transistors Q11 and Q21 of the sense amplifier SA10 respond to the setting of the threshold voltage correction control signal OCV1 to the reference level to sense the levels of the respective bit lines BL11 and BL12.
Thereafter, a read control signal RS1 is set to an active level. In response to the setting of the read control signal RS1 to the active level, the transistors Q13 and Q23 of the sense amplifier SA10 are turned on and transmit the levels of the bit lines BL11 and BL12 detected by the detecting transistors Q11 and Q21 to the respective common bit lines GBL1 and GBL2. A common sense amplifier GSA amplifies a potential difference between the common bit lines GBL1 and GBL2 up to a full amplitude and outputs it externally.
Then, in the re-write period T4, a write control signal WS1 is made active. In response to the activation of the write control signal WS1, the transistors Q14 and Q24 of the sense amplifier SA10 are turned on, so that the fully amplified voltage levels on the common bit lines GBL1 and GBL2 are transmitted to the respective bit lines BL11 and BL12 and re-written in the memory cell C11 selected by the word line WL11.
In this semiconductor memory device 300, the voltage levels of the bit lines BL11 and BL12 are corrected according to the threshold voltages of the detecting transistors Q11 and Q12 before the data stored in the memory cell is read out. Therefore, it is possible to maximize the magnitude of voltage level variation of the bit lines with respect to the threshold voltages of the transistors Q11 and Q12 at the time when data stored in the memory cells C11 and C12, etc., are read out and thus the problem of reduction of S/N and sensitivity is solved.
Further, as mentioned previously, since the bit lines BL11, BL12, BL21 and BL22 are formed in the layer other than the layer in which the common bit lines GBL1 and GBL2 are formed and the sense amplifiers SA10 and SA20 are constructed with NOM type transistors only, it is possible to reduce an occupation area thereof.
FIG. 7 is a circuit diagram of an example of the threshold voltage correction/read operation driver circuit OCD. In FIG. 7, the driver circuit OCD comprises an NMOS transistor Q9 having commonly connected gate and drain supplied with a boosting level VXD, an NMOS transistor Q10 having a drain connected to a source of the transistor Q9, a source connected to ground potential and a gate supplied with the control signal RS1, an NMOS transistor Q7 having a drain supplied with a threshold value correcting voltage OVV, a gate connected to the source of the transistor Q9 and a source from which the driver output voltage OCV1 and an NMOS transistor Q8 having a drain connected to the source of the transistor Q7, a source connected to ground potential and a gate supplied with the control signal RS1.
An operation of the driver circuit OCD will be described with reference to FIG. 7. For the threshold voltage correcting operation, the read operation control signal RS1 is set to an active level. In response to the read operation control signal RS1 in the active level, the transistor Q10 is turned off to thereby set a potential of the gate of the transistor Q7 to H level. In response to the level change of the gate potential to H level, the transistor Q7 is turned on to make the driver output voltage OCV1 to the threshold value correction voltage OVV.
For the read operation, the read operation control signal RS1 is set to active level to turn the transistor Q10 on. Thus, the gate of the transistor Q7 is supplied with a level determined by a ratio of size, that is, current drive ability, between the transistors Q9 and Q10. Since the current drive ability of the transistor Q10 is set higher than that of the transistor Q9, the transistors Q7 and Q8 are turned off and on, respectively, when the read control signal RS1 is in the active level, and so the driver output voltage OCV1 becomes ground potential.
Since, in this driver circuit, the output current is substantially restricted by the current drivabilities of the transistors Q7 and Q8 in the output stage, there is a problem that the threshold value correction and the read operation take considerable times, respectively, and the speed-up of the data access is difficult. Assuming the division number of the memory cells in the conventional semiconductor memory device 300 described above is, for example, 256, 256 sense amplifiers commonly use one threshold correction/read operation driver OCD. Since, as mentioned above, the output current of this driver circuit is substantially restricted by the current drivabilities of the output stage transistors, there is the problem that the threshold voltage correction and the read operation take considerable times, respectively, and the speed-up of the data access is difficult.
Further, since the current flows through the series connected transistors Q9 and Q10 of the output drive stage during the read operation period, reduction of current consumption of the chip is difficult.